1. Field of the Invention
The present invention relates to an annealing technology in a process for manufacturing a semiconductor device. More particularly, the present invention relates to a method for manufacturing a semiconductor device which can reduce the number of fabrication steps and then improve the controllability of impurity distribution profile and further accomplish the improved electrical characteristics, and a equipment for executing this method.
2. Description of the Related Art
A process for manufacturing a semiconductor device, such as an LSI and the like, is provided with a designing step, a mask preparing step, a wafer producing step, a wafer treatment step, an assembling step, an inspecting step and the like. The product is formed through these various steps. Among them, the wafer treatment step (hereafter, this is referred to as "a wafer process") is a main technique when the semiconductor device, such as the LSI and the like, is developed and manufactured. The wafer process is constituted by the complex combination of the various fabrication steps listed below:
(a) a film forming step, such as chemical vapor deposition (CVD), epitaxial growth, thermal oxidation and the like; PA1 (b) a photolithography step; PA1 (c) an etching step, such as wet etching, and dry etching including as reactive ion etching (RIE) and the like; PA1 (d) an impurity doping step, such as thermal diffusion, ion implantation and the like; PA1 (e) a planarizing step, such as chemical mechanical polishing(CMP) and the like; or PA1 (f) a wafer cleaning step.
Then, in order to attain the performance in accordance with the design of the objective semiconductor device, it is necessary to precisely control the vertical dimensions of thicknesses of various films and the like (the dimensions in the thickness direction), the lateral dimensions of gate lengths and the like (the dimensions in the plane direction), the impurity distribution profile and the like. However, a phenomenon is known in which the impurity diffusion is enhanced or suppressed by a damage (hereafter, referred to as "a primary defect") of a semiconductor substrate induced by the ion implantation used in the impurity doping step. Moreover, a fact is also known in which because of this damage, a defect (hereafter, referred to as "a secondary defect") such as a dislocation is induced by the next annealing and this defect causes the crystallographic deterioration, such as the increase of leakage current and the like. In order to recover the primary defect induced at the time of the ion implantation and the like, it is effective to execute a high temperature annealing by a rapid heating up step with an infrared (IR) lamp annealing or the like. Thus, a method of executing the IR lamp annealing after the ion implantation is conventionally used. Hence, in an actual wafer process, for example, after the ion implantation, several annealing steps are executed for the sake of the activation of the ion implantation as well as the recovery of the damage. After these fabrication steps, in the LSI technology, the thermally oxidizing step is executed to form a gate insulating film.
FIG. 1 shows a schematic view of a temperature history of a wafer when the thermally oxidizing step is executed by using a resistive heating furnace in accordance with a conventional technique. In FIG. 1, T.sub.2 and .tau..sub.2 denote a process temperature and a process time in the resistive heating furnace, respectively. In the case of the thermally oxidizing step, the T.sub.2 is set to be a temperature region in a range between 700.degree. C. and 1000.degree. C., and the .tau..sub.2 is set between several minutes and several hours. In the example shown in FIG. 1, a heating and cooling rate of the resistive heating furnace is assumed to be 50.degree. C. per minute. However, there may be a case that the heating and cooling rate is stepwise changed depending on the temperature region of the heating and cooling operation. Moreover, a rate in a range between 1.degree. C. per minute and 100.degree. C. per minute is typical as the heating and cooling rate. However, there may be a case that the heating and cooling operation is executed at a faster speed or a slower speed than the above mentioned rate.
Conventionally, if the IR lamp annealing step is added for the sake of the activation of the implanted ion and the recovery of the damage after the ion implantation, a problem is brought about which drops a manufacturing efficiency of a product associated with the increase of the number of the annealing step. This problem is brought about by the troubles described below. That is, the frequency of raising and lowering the substrate temperature is increased in conjunction with the increase of the annealing step, which leads to the thermal fatigue of the semiconductor substrate resulting from the development of structural defect, the occurrence of micro defect such as oxygen precipitation and the like. As a result, the structural defect, the micro defect and the like cause the problem of the deterioration of the electric performance of the semiconductor device.
On the other hand, a method of consecutively executing the annealing step and the thermally oxidizing step by the rapid thermal annealing (RTA) operation with an IR lamp heating furnace may be considered as a promising scheme of avoiding the increase of the number of the annealing steps. Although the IR lamp heating furnace is advantageous to a locally heating operation, due to the nature of the IR lamp heating furnace, it is difficult to attain the uniform temperature distribution. Now, the utilization of a silicon wafer having a diameter of 300 mm is reviewed. In the annealing using such a large wafer, it is difficult to attain the uniformity of the temperature distribution, even if using a single wafer type IR lamp heating furnace.
Since the single wafer type IR lamp heating furnace has a problem of poor productivity, a batch type IR lamp heating furnace may be desirable which can process a plurality of silicon wafers at the same time. However, it is extremely difficult to attain the uniformity of the temperature distribution, if using the batch type heating furnace. Thus, if the plurality of silicon wafers are thermally oxidized at the same time by using the IR lamp heating furnace, this results in a problem that it is difficult to form an silicon oxide film having the uniform film thickness within the wafer surface. In particular, it is known that the oxidizing step executed in wet O.sub.2 ambient is suitable for the formation of the silicon oxide film having the excellent quality such as a high breakdown voltage and the like. However, this has a problem that the accumulation of water drops on an inner wall of a reaction tube causes the irregularity of the transmission of the IR radiation. Moreover, this causes a trouble that it is difficult to form the silicon oxide film having the uniform film thickness within the wafer surface.
As mentioned above, it is difficult to simultaneously execute the recovery of the damage and the formation of the excellent and uniform silicon oxide film by only using the IR lamp heating furnace. It is especially difficult to simultaneously execute the recovery of the damage and the formation of the excellent silicon oxide film, for the plurality of large diameter silicon wafers. This results in a problem of a poor throughput.